Chipset architecture used to be split into two main chips: the Northbridge for fast stuff like the CPU and RAM, and the ...

A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...

JEDEC is still finalizing the HBM4 memory specifications, with Rambus teasing its next-gen HBM4 memory controller that will be prepared for next-gen AI and data center markets, continuing to expand ...

Integrated circuit company Montage Technology has launched its CXL 3.1 Memory eXpander Controller (MXC), which is currently being tested by some of its key customers, including AMD and Intel. The ...

As artificial intelligence (AI), machine learning (ML), cloud computing, and data analytics take on a greater role, traditional processors are starting to see the limits of processing efficiency from ...

The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...