Last month, I started to explore when to use simple sequences and when to use complex sequences. Part of creating the correct sequence lies in the proper use of technology. For example, let’s look at ...
The SystemVerilog universal verification methodology (UVM) is an efficient way to generate tests and check results for functional verification, best used for block level IC or FPGA or other “smaller” ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback