Semiconductor Engineering

Research Bits: Jan. 27

Researchers from Politecnico di Milano, Peking University, and Hewlett Packard Labs developed a Closed-Loop In-Memory ...
IEEE

A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration

Abstract: This article presents a 7-bit, 1.15-GS/s, 2.6-bit/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that incorporates a comparator decision skip ...
IEEE

FPGA-based Medical Image Processing Using Hardware-Software Co-design Approach

Abstract: This paper presents a field-programmable gate array (FPGA) based medical image processing framework using a hardware-software co-design approach for biomedical tasks such as Malaria and ...